Kharkov National University of Radioelectronics
نویسندگان
چکیده
Single event upsets (SEU) produced by heavy ions in SOI CMOS SRAM cells were simulated using a mixed-mode approach, that is, two-dimensional semiconductor device simulation by TCAD tool coupled with circuit SPICE simulator. The effects of parasitic BJT and particle strike position on the SOI CMOS SRAM cells upset for transistor length scaling from 0.25 um to 65nm are presented.
منابع مشابه
Kharkov National University of Radioelectronics
The corrections of the methodology of power BJT and MOSFET transistor models parameter extraction taking into account the self heating effects are presented For BJT these corrections are included into VBIC model parameter extraction process. For MOSFET current generator connected to standard SPICE MOS model is proposed to take into account drain current growth with transistor temperature.
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